1. Field of the Invention
The present invention relates to a block select circuit in a flash memory device, and more particularly, to a select circuit in a flash memory device which enables a fail block to be processed even after being packaging by means of only an operation of programming the flash memory cell of an erase state so that a given voltage is not applied to the fail blocks.
2. Background of the Related Art
FIG. 1 is a block select circuit in a conventional NAND type flash memory device.
The block select circuit includes a select unit 11 for outputting a block select signal B_Sel according to an address signal and a select signal SEL, a high-voltage pumping unit 12 for outputting a signal to keep a given high voltage according to the output signal of the select unit 11 and a clock signal, and a switching unit 13 for applying a given bias to a gate select line GSL, a word line WL and a source select line SSL of a flash memory cell block 14 according to the output signal of the high-voltage pumping unit 12.
First, the construction of the select unit 11 will be described. A first NAND gate 101 logically combines 0˜seventh address signals inputted from a first address input terminal ADx[0:7], eighth˜fifteenth address signals inputted from a second address input terminal ADx[8:15], and sixteenth twenty-third address signals inputted from a third address input terminal ADx[16:23]. A fuse F11 is connected between the output terminal of the first NAND gate 101 and a first node Q11. A first PMOS transistor P11 having a gate terminal connected to the ground terminal Vss is connected between the power supply terminal Vcc and the first node Q11. A NOR gate 102 logically combines the potential of the first node Q11 and the select signal SEL to output a block select signal B_Sel.
Next, the construction of the high-voltage pumping unit 12 will be described. A second NAND gate 103 logically combines the clock signal Clk and the output signal of the NOR gate 102. A first NMOS transistor N11 driven by the power supply voltage Vec is connected between the output terminal of the NOR gate 102 and a second node Q12. A first capacitor C11 that is charged according to the output of the first inverter I11 for inverting the output signal of the second NAND gate 103 is connected between the output terminal of the second NAND gate 103 and the second node Q12. A second NMOS transistor N12 driven according to the potential of the second node Q12 is connected between the second node Q12 and a pumping terminal Vpp. A fourth NMOS transistor N14 driven by the potential of the second node Q12 is connected between the pumping terminal Vpp and a third node Q13. A second capacitor C12 is connected between the output terminal of the second NAND gate 103 and the third node Q13. A third NMOS transistor N13 is connected between the third node Q13 and the second node Q13.
The construction of the switching unit 13 will be now described. A fifth NMOS transistor N15 supplies a given voltage V_GSL to the gate select line GSL of the flash memory cell block 14 according to the output signal of the high-voltage pumping unit 12. A sixth NMOS transistor N16 supplies a given voltage V_WL to the word line WL of the flash memory cell block 14 according to the output signal of the high-voltage pumping unit 12. Furthermore, a seventh NMOS transistor N17 supplies a given voltage V_SSL to the source select line SSL of the flash memory cell block 14 according to the output signal of the high-voltage pumping unit 12. Meanwhile, an eighth NMOS transistor N18 is driven according to the block select signal B_Sel that is inverted through a second inverter 112 to apply a given voltage V_GSL′ to the gate select line GSL of the flash memory cell block 14 that is not selected.
A method of driving the conventional block select circuit in the flash memory device constructed above will be now described.
If a block is not selected, the address signals inputted through the first˜third address input terminals ADx are applied with a Low state. The first NAND gate 101 then logically combines those signals to output a signal of a High state. The output signal of the first NAND gate 101 that is kept as the High state is applied to the first node Q11 via the fuse F11, so that the first node Q11 keeps the High state. As the potential of the first node Q11 that keeps the High state and the select signal SEL applied as the High state because the block are not selected, the NOR gate 102 logically combines the potential of the first node Q11 and the select signal SEL to output the block select signal B_Sel of a Low state. Meanwhile, if a block is selected, the address signals inputted through the first˜third address input terminals ADx are applied as a High state. The first NAND gate 101 then logically combines those signals to output a signal of a Low state. Therefore, a current path to the ground terminal Vss through the fuse F11 and first NAND gate 101 is established. As the amount of the current applied through the first PMOS transistor P11 is larger than that passed to the ground terminal Vss, the first node Q11 keeps the potential of the Low state. Furthermore, if a block is selected and the circuit is thus driven, however, as signals of a Low state are applied but the circuit is not driven, the NOR gate 102 outputs the block select signal B_Sel of a Low state when the select signal SEL is applied as a High state. The second NAND gate 103 that received the block select signal B_Sel of the Low state and the clock signal Clk keeps the High state regardless of the clock signal Clk. Accordingly, the first capacitor C11 and the second capacitor C12 do not perform charge operations and the block select signal B_Sel is at a Low state. Therefore, as the second node Q12 becomes 0V through the first NMOS transistor N11, the fifth˜seventh NMOS transistors N15˜N17 of the switching unit 13 are turned off. Meanwhile, the block select signal B_Sel applied as a Low state is inverted to a High state through the second inverter 112 and the eighth NMOS transistor N18 is then turned on by this potential. Therefore, the voltage V_GLS′ is applied to the gate select line of a not-selected block.
If a block is selected, the address signals inputted through the first˜third address input terminals ADx are applied as a High state. The first NAND gate 101 then logically combines those signals to output a signal of a Low state. Thereby, a current path to the ground terminal Vss through the fuse F11 and the first NAND gate 101 is established. As the amount of the current applied through the first PMOS transistor P11 is smaller than that passed to the ground terminal Vss, the first node Q11 keeps the potential of the Low state. If the potential of the first node Q11 that keeps a Low state and the select signal SEL applied as the Low state because the block are selected, the NOR gate 102 logically combines the potential of the first node Q11 and the select signal SEL to output the block select signal B_Sel of a High state. The second NAND gate 103 that received the block select signal B_Sel of the High state and the clock signal Clk receives an inverted signal of the clock signal Clk. This repeatedly charges and discharges the first capacitor C11 and the second capacitor C12 and thus makes the second node Q12 to have a potential higher than Vpp. Furthermore, as the second node Q12 keeps a given potential (Vpp+Vt) by means of the second NMOS transistor N12, the first NMOS transistor Nil is turned off. Therefore, the fifth˜seventh NMOS transistors N15˜N17 of the switching unit 13 are turned on, by the potential of the second node Q12, to apply a given voltage V_GSL to the gate select line GSL, a given voltage VWL to the word line WL, and a given voltage V_SSL to the source select line SSL, of the flash memory cell block 14. Meanwhile, the block select signal B_Sel applied as a High state is inverted into a Low state through the second inverter 112. As the eighth NMOS transistor N18 is then turned off by the potential of the Low state, the voltage V_GLS′ is not applied to the gate select line of a not-selected block.
In the conventional block select circuit constructed and driven as above, the block select signal B_Sel must keep a Low state regardless of the address signal in order to permanently define any fail flash memory cell block as a fail block. For this, it is required that the fuse is physically disconnected so that the potential of the first node always keeps a High state. However, the process of physically disconnecting the fuse is possible in a wafer status but it is impossible in a package state. Due to this, it is impossible to define any fail block occurring in a subsequent test as a fail block physically.